A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance
A Low-Phase Noise, Low-Power PFD Circuit Using GDI and Pass Transistor Logic with PVT tolerance uses only 9 transistors ? Are there any shortcomings ?
Someone told me :
The proposed GDI/PTL-based PFD design suffers from weak signal integrity, specifically threshold voltage drops, which can cause significant leakage current in the charge pump. Furthermore, the design has reduced driving capability, resulting in slower edges and poor performance in driving capacitive loads, often requiring additional buffering to function effectively in a PLL.
It could also lead to floating output nodes, increased PVT sensitivity, and design complexity that may result in higher dead zones, asymmetry, and increased jitter.
Could anyone advise further ?
Posted Apr 5, 2026, 3:01 PM UTC