Vivado synthesis tool for SystemVerilog

Since EDA playground couldn't synthesize SystemVerilog codes. I used Vivado synthesis tool to run my codes. I used systemVerilog (always_ff, for loop, logic key word etc) as my design language, and synthesis is successful.

However, when I go to project settings, I only have two choices for the target language: Verilog/VHDL. The default in my case is Verilog.

So, there is a conflict here regarding the HDL language used. I picked up systemVerilog when this file was created, but the target language in the settings section has to be Verilog.

Any comments on this HDL discrepancy for the same project?