Looking for referrals in VLSI

Role: Entry-Level ASIC Physical Design / RTL Design / Physical Verification.

I’m a 2026 ECE graduate seeking full-time
opportunities.
My experience includes:

RTL-to-GDSII using Cadence Innovus

OpenLANE & SKY130 ASIC flow

Physical Verification (DRC/LVS), STA

Verilog, SystemVerilog, TCL, Linux

FPGA prototyping and RISC-V-based projects

Internships in ASIC Physical Design and Embedded Systems

I’m actively building my VLSI portfolio with end-to-end projects and GitHub documentation. If your company is hiring fresh graduates or you’re able to provide a referral, I’d greatly appreciate it.
I’m happy to share my resume and GitHub via DM.

Thank you for your time!