TLAST deasertion in verilog-ethernet 10G UDP IPfrom Alex Forencich when transmitting data.

Hi everyone,

I am using Alex Forencich's IP core (https://github.com/alexforencich/verilog-ethernet) on an AMD ZCU106 board. I am not using the internal loopback, but rather an actual data stream (currently around 40 MB/s). My goal is to increase this throughput and get closer to the maximum line rate (10G over SFP+).When sending a UDP packet, I wait for the UDP_HDR_READY signal to go high ('1') and then assert the UDP_HDR_VALID signal for exactly one clock cycle. As I understand it, this latches the ports and IP addresses. Simultaneously, I assert the TVALID signal on the AXI-Stream interface and wait for the TREADY assertion. At the end i assert TVALID. Everything works perfectly when sending smaller amounts of data. However, when I increased the payload size to 1008 bytes (1000 bytes of data + 8 bytes of UDP header), the TREADY signal deasserts after exactly 100 transmitted 64-bit words.Has anyone encountered a similar issue? What could be the potential cause and solution for this behavior?

Thanks in advance for your help!

tag:

u/alexforencich