HDL BITS website giving unexpected output on the dual edged flipflop problem.

https://preview.redd.it/14jein4vbqih1.png?width=689&format=png&auto=webp&s=2f695644185682d88a8e2980f88eb1f13311da21

so the link for the question is this https://hdlbits.01xz.net/wiki/Dualedge

In all other previous questions, there was some propagation delay when i used posedge in the sensitivity list with clock, but here there is no propagation delay., why ?

The code is simple

always@(clock)
q<=d ;