VLSI

Working on a VLSI course final project: a 4-bit parity generator/checker with an FSM control block on top (IDLE → GENERATE mode / CHECK mode → MATCH/ERROR states, 2-always-block coding style).
Setup:
• Functional sim in ModelSim (waveform verification)
• Synthesis + timing-driven place & route through OpenLANE, targeting the sky130 PDK
• Need to hit timing closure and read an OpenSTA report afterward
This is my first time taking a design all the way through OpenLANE instead of just simulating it. A few things I'd appreciate input on:
1. Any gotchas when moving from a ModelSim-verified netlist into the OpenLANE flow (config.json setup, clock constraints in the SDC file)?
2. For a small FSM + parity design like this, what's a realistic starting CLOCK_PERIOD to avoid early negative slack?
3. Any recommended reference for writing a clean SDC file for a first-timer?
Happy to share the RTL if useful. Thanks in advance!