Source
r/yosys•
bluesilicon

Synthesized edif netlist with cell name as $_DFF_PN0_, $_DFF_PN1_ and $_DFF_P_

The synthesized edit netlist has the cell $DFF_PN0, $DFF_PN1 and $DFF_P definitions. I don't quite understand the meaning. What I can understand is DFF with negative trigger, with enable, set, reset, sync, async. Is there a mapping between the cell name and the function?

The definition in EDIF as follow:

(cell (rename id00001 "$_DFF_PN0_")
  (cellType GENERIC)
  (view VIEW_NETLIST
    (viewType NETLIST)
    (interface
      (port C (direction INPUT))
      (port D (direction INPUT))
      (port Q (direction OUTPUT))
      (port R (direction INPUT))
    )
  )
)
(cell (rename id00002 "$_DFF_PN1_")
  (cellType GENERIC)
  (view VIEW_NETLIST
    (viewType NETLIST)
    (interface
      (port C (direction INPUT))
      (port D (direction INPUT))
      (port Q (direction OUTPUT))
      (port R (direction INPUT))
    )
  )
)
(cell (rename id00003 "$_DFF_P_")
  (cellType GENERIC)
  (view VIEW_NETLIST
    (viewType NETLIST)
    (interface
      (port C (direction INOUT))
      (port D (direction INOUT))
      (port Q (direction INOUT))
    )
  )
)

Posted Dec 6, 2014, 12:40 AM UTC

210
CliffordVienna•

Yes, there is a mapping between cell name and function.

Chapter 5 ("Internal Cell Library") of the Yosys manual contains a description of this cell types. See Table 5.3 on page 40 of the current version of the manual: http://i.imgur.com/xaAiKWe.png

The Verilog file simcells.v contains simple Verilog simulation models for the internal gate-level cells (see simlib.v for simulation models of RTL cells).

Usually you would use either "techmap" (with a custom map file) or "dfflibmap" (with a cell library in liberty format) to convert the internal flip-flop types to the flip-flop types of your target architecture before writing an EDIF file with your netlist. Similarly you'd use "techmap" or "abc -liberty" to convert non-flip-flop cells to the cell types of your target architecture.

1
bluesiliconOP•

Thanks for the explanation. It does help! I went through the cell library, and I didn't see the type of DFF with enable in your library. We have such DFF with enable in our design. Could you please shed some light on how to support the DFFE type of dells. The verilog behavior of the DFFE is as follow:

module DFFE (Q, C, E, D); input D, C, E; output Q; assign (weak0, weak1) E =1'b1 ; reg Q = 0; always @(posedge C) if (E) Q <= D; endmodule

1
CliffordVienna•

Yes, DFFE cells are not supported atm. There are on the to-do list and I will prioritize them now.

The problem is of course not adding the cell types itself (that's easy) but adding the code necessary to create those cells from a given circuit and handle a specific clock+en signal combination like a separate clock domain for things like retiming.

1
CliffordVienna•

Ok, I've now added very basic DFFE support so you have something to work with..

The new command "dff2dffe" will replace $dff cells with $dffe cells, when appropriate. Then "techmap" will convert them into $_DFFE_??_ cells. At the moment retiming of DFFE cells is not supported. The "dfflibmap" command also does not supprt DFFE yet. But it's a start.. ;)

Here is an example script that will create a circuit with a $dffe cell in it:

read_verilog <<EOT
  module counter (clk, rst, en, count);
    input clk, rst, en;
    output reg [7:0] count;
    always @(posedge clk)
      if (rst)
        count <= 2'd0;
      else if (en)
        count <= count + 2'd1;
  endmodule
EOT

proc
dff2dffe
opt -full
show

The output of that script looks like this: http://i.imgur.com/eWsBdeN.png

1
bluesiliconOP•

Thanks a lot! I guess I have to download the new executable. When will the new Yosys ready to be downloaded?

1
CliffordVienna•

Here is the win32 binary for the latest git head. I've just cross-compiled it, not actually tested it. So it might very well be that you will find new bugs in this version.. ;)

http://scratch.clifford.at/yosys-win32-mxebin-0.4+28.zip

1