Feedback on a PCB design with mixed RF (xpost r/PrintedCircuitBoard)

Hello everyone,

I have been working on a fairly small PCB (4x5cm) that includes a GPS receiver module (ublox max-7q), a BLE antenna, and a few buses. I have been trying to figure out the best way to separate components to reduce noise and below is my take on it. A previous variation used a chip antenna for GPS and a chip antenna for BLE and nothing worked -- I believe I messed up the matching circuit for the GPS antenna and I'm not sure I needed the LNA that I used. I updated that design with a much bigger patch antenna for GPS (on the back of the board) and updated the BLE balun.

An image of my PCB is here: http://imgur.com/6ELY3kr

Some notes:

  1. The lower third of the board is voltage regulation and a SMPS.
  2. The MCU is the chip in the middle; with a few sensors to the left.
  3. BLE is top right.
  4. GPS patch antenna is selected and is on the top left of the board; it's going to be on the reverse side. I tried to not run any signals around the antenna, but could not give it enough space from signal.
  5. Green layer is the back of the board, red is front, layer 2 (not visible) is a ground plane, layer 3 is power.
  6. I plan on disabling BLE when GPS is in use for the most part, but the two can and will likely overlap.

I am planning on adding via stitching to most of the board, especially under the surface of the GPS antenna. I'm also filling in both top and bottom layers with a ground fill. The ground plane is fairly uninterrupted, save for the vias.

Now on to a few specific questions:

  1. Right now, I have the RF feed of the GPS antenna /right/ next to the feed of the module. i first used an impedance calculator, but decided to just give it a fat (15-20mil) trace between the feed and the module; since the keep-out area of the pin hole removes the ground plane below the trace and the distance is about 0.25mm, my plan is to just leave it as a fat trace. Does that make sense?
  2. Should I break up the ground plane around the antenna and stitch it in places, or use the entire ground plane?
  3. Should I bother with adding a SAW filter between the antenna and the module? Due to size constraints it might push the antenna closer to the noisy parts of the circuit, but the ublox doesn't have an internal one.
  4. Can I change something about the current design (esp size constraints) to make it friendlier for the RF portions?

Thanks in advance for any feedback!

Posted Oct 19, 2015, 4:12 AM UTC · edited

121
electric_machinery•

It looks like C18 is an RF bypass cap. You can/should use multiple vias to ground and use the most minimal trace length to the via. See Xilinx's appnote on bypassing caps for the best possible solutions.

That's probably not an issue though. It looks decent as far as I can tell.

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