A couple questions regarding phase locked loops

Hi, I'm designing a phase locked loop in labview FPGA. I've managed to have the signal lock in, but I feel like I'm missing some fundamentals about PLL's.In addition to the PLL, I have managed to design a frequency detector that works decently, and I was wondering if it made any sense to hook up the detected frequency to my VCO's free running frequency input (In my mind this makes sense because this could get the PLL locked into any frequency, not just a predetermined range). Finally, I was also wondering about the loop filter. I am using a low pass butterworth filter with a corner frequency of 40Hz. I believe I understand the point of the filter in the circuit, but I'm not sure how to decide what the cutoff should be - what is the deciding factor? All this being said, I've only learned about PLLs from google searches, so any help is appreciated. Thanks