r/RISCV

8.3K archived posts · May 2015 – Sep 2026

The RISC-V Instruction Set Architecture

r/RISCV

RISC-V (pronounced "risk-five") is a license-free, modular, extensible computer instruction set architecture (ISA). Originally designed for computer architecture research at Berkeley, RISC-V is now used in everything from $0.10 CH32V003 microcontroller chips to the pan-European supercomputing initiative, with 64 core 2 GHz workstations in between. RISC-V is suitable for custom silicon chips, as a soft core in an FPGA, or as a high performance software Virtual Machine. riscv.org

Created Apr 23, 2015

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