TL;DR: Since I have not found 64-bit multiplication (signed or unsigned) or unsigned division/remainder circuits online, I thought I might share.

BP Book: https://factoriobin.com/post/n95djb

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A little bit of background: I'm building a Risc-V computer, since I have done custom CPUs before and wanted to try implementing a real Instruction Set Architecture (ISA). That [one guy from CCC](https://media.ccc.de/v/39c3-cpu-entwicklung-in-factorio-vom-d-flip-flop-bis-zum-eigenen-betriebssystem) also gave me the push to finally start doing it.

I also want to include the M extension, which includes some multiplication instructions:

- `mul`, `div` and `rem`: these to the same thing the `*`, `/` and `%` operators do in Factorio: multiply, divide and get remainder or **signed** 32-bit integers.
- `mulh`, `mulhsu` and `mulhu`: these get the high 32 bits of a multiplication result, and they treat the operands as **signed x signed**, **signed x unsigned** and **unsigned x unsigned**, respectively.
- `divu` and `remu`: these divide and get remainder or 32-bit **unsigned** integers.

### Multiplication

Multiplications of 2 N-bit numbers produces 1 2N-bit number, but Factorio cannot represent 64-bits in a signal, so it discards the high 32 bits.

That behavior is exactly what we want for the `mul` instruction, the low bits of a signed multiplication.

For the other instructions, we need to use long multiplication. For example, treating groups of 16 bits as "digits":

```
We want to do: 0x1234 5678 * 0x8765 4321 = 0x09A0 CD05 70B8 8D78

Operands:
A = 0x1234 5678
B = 0x8765 4321

"Digits":
AL = 0x5678
AH = 0x1234
BL = 0x4321
BH = 0x8765

Operation:
      AHAL
*     BHBL
----------
      AL*BL
    AH*BL 0
    BH*AL 0
+ AH*BH 0 0
-----------
     Result

Actual calculation:

0x5678 * 0x4321 = 0x16AC8D78

0x1234 * 0x4321 = 0x04C5F4B4

0x5678 * 0x8765 = 0x2DBB6558

0x1234 * 0x8765 = 0x09A09A84

Final sum:
09A0 9A84
     2DBB 6558
     04C5 F4B4
+         16AC 8D78
-------------------
09A0 CD05 70B8 8D78

```

We can turn 32-bit integers into 16-bit ones with either bit-masking (`A & 0xFFFF = AL`) or bit shifting (`A >> 16 = AH`).

With some bit-masking we can keep those high 16-bits unsigned, so Factorio actually treats them as unsigned, or we can leave them to get signed multiplication. This is shown in the second image on the left, note that S1H and U1H only differ in that the former starts with FFFF.

### Division

The main idea for unsigned division is to split the dividend into two parts: the one with the sign bit and the other one, which is easily done with 2 bit masks. The same applies to unsigned remainder.

From there, there are some off by one errors and different special values depending on which operand is negative.

Division by 0 and signed overflow (-2.1G / -1) are implemented as Risc-V defines [here](https://docs.riscv.org/reference/isa/unpriv/m-st-ext.html#12-1-2-division-operations).

### How to use

These instructions are part of the `OP` opcode, which has two more fields to define the instruction used: F3 and F7. For these operations, F7 must be 1 (encoded in the 7-signal). F3 (encoded in the 3-signal) switches between the operations `mul` through `remu` with values 0-7.

The operands are in the 1-signal and 2-signal. The four signals are in the CCs in the top of the first image.

***NOTE***: I make heavy use of the Nixie Tubes mod to display unsigned hexadecimal numbers as the operands and results, and Text Plates to label components, but they are not needed for the computation and thus optional.

### Performance

`mul`, `div` and `rem` take only 2 ticks, as they are built in.

`mulh[s[u]]` take 5 ticks.

`divu` takes 4 ticks.

`remu` takes 7 ticks.

Maybe this inspires some golfers to minimize these circuits or shorten the delay?

64-bit multiplication and unsigned 32-bit division