Echo-Server as Block-Design on a Diligent Arty A7-35

Hi everyone! I'm new to FPGA stuff and I'm really struggling to find a solution to my problem. I've got an Arty A7-35 development kit from Digilent. I have to use an FPGA to transport data from the pin-header via Ethernet (UDP) to the computer. I came across this open-source core on GitHub (https://github.com/alexforencich/verilog-ethernet) which seems to fit the bill nicely! It's written in Verilog. So, my first step was to try out the Echo-Server example and then create blocks from it, as I was kindly advised to do.

My system is openSUSE Tumbleweed and I use Vivado 2024.1.2.

I made a few changes to the Verilog files:
udp_complete: I found that the ARP_REQUEST_TIMEOUT number was a bit too big, so I wrote the keyword 'time' in advance of the parameter to make it work.
eth_axis_rx/tx: The program said not all variables have an initial value, so I copied them to the global path of the file to make it work.

In the constraint file I commented out:
#set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
Because I throw an error

My problem is that my server doesn't send me back on that layer, but when the whole core is in one block it is working perfectly. I have no errors.

For requests, I am at your service and hope it is just a wire I didn't connect right.

My block diagram

The Verilogfiles that I used