Hi everyone! I'm new to FPGA stuff and I'm really struggling to find a solution to my problem. I've got an Arty A7-35 development kit from Digilent. I have to use an FPGA to transport data from the pin-header via Ethernet (UDP) to the computer. I came across this open-source core on GitHub (https://github.com/alexforencich/verilog-ethernet) which seems to fit the bill nicely! It's written in Verilog. So, my first step was to try out the Echo-Server example and then create blocks from it, as I was kindly advised to do.
My system is openSUSE Tumbleweed and I use Vivado 2024.1.2.
I made a few changes to the Verilog files:
udp_complete: I found that the ARP_REQUEST_TIMEOUT number was a bi
60