Three Lessons from Building My Own RISC-V Processor, ucrv32

Hey everyone,
I recently completed my simple RISC-V processor project, ucrv32, featuring a 5-stage pipeline architecture. Throughout the process, I learned three practical lessons: the necessity of careful design planning, the value of thorough test benches, and the benefits of grouping signals using interfaces.

I’ve shared these lessons in detail on my blog, and I think they offer useful insights for anyone interested in digital design and computer architecture. Check it out and let me know what you think!

https://leftarcode.com/posts/first-riscv-lessons/