Hello  I wanted to share my university final year project. It is a RV32I Zicsr Zicfilp Smcfiss Smpmpnd 5 stage pipelined SoC\*. I personally only have a Tang Primer 20k and only the baseboard (DDR3 interface). Hence the communication is completely over UART. The CPU has been verified with RISCOF for RV32I. I have also bootstrapped C with newlib and ported UART playable games like Tetris and Pong.

Since simply 5 stage pipelined CPUs are quite common nowadays, I wanted to explore more Security aspects in hardware. Hence I went ahead and implemented CFI protection with Zicfilp (Landing Pads) and Smcfiss with Smpmpnd (Shadow Stack Draft Extensions). Since Zicfiss require MMU enabled CPUs, I found this draft which I instead implemented.

https://github.com/ved-rivos/riscv-isa-manual/blob/smpmpss/src%2Fsmcfiss.adoc

I also built the GNU toolchain for my extensions combo and everything is managed with Nix for easy development. I found a bug in Newlib for Zicfilp and sent a patch (My first open source patch in a relatively big project so I feel quite good abt it).

I understand RISC-V cores are an oversaturated project but I hope you like it. Let me know any improvements I could do. I had bigger plans but require upskilling in other aspects to get a job, but I will not be letting go of this project.

eSC-V: Machine-Mode CFI-Hardened RISC-V SoC in VHDL